Problem with Modelsim simulation

[liuguangxi]

I found there are some minor bugs when build simulation using Modelsim:

(1) In the file e203_soc_top.v
`include "e203_defines.v" was omitted in the very begin,
which caused definitions of macros missing in the codes.

(2) In the file tb_top.v
line 270: $readmemh({testcase, ".verilog"}, itcm_mem);
Seems #0 would be added in the beginning:
#0 $readmemh({testcase, ".verilog"}, itcm_mem);
or there may exists race hazard with $value$plusargs statement.