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1. RV32I-5-Stage-Processor RV32I-5-Stage-Processor Public

   A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests…

   SystemVerilog 3

2. RV32I-Single-Cycle-Processor RV32I-Single-Cycle-Processor Public

   A SystemVerilog implementation of a single-cycle processor for the RV32I base ISA of RISC-V. Designed for simplicity and clarity, this CPU executes one instruction per clock cycle and includes full…

   SystemVerilog

3. UART UART Public

   SystemVerilog implementation of a UART Transmitter and Receiver with a 9600 baud Baud Generator using a 50 MHz clock. Sends and receives 8-bit data MSB-first.

   SystemVerilog

4. SystemVerilog-Practice SystemVerilog-Practice Public

   This repository contains a collection of basic digital design components implemented in SystemVerilog, along with their corresponding testbenches. Each module demonstrates a key concept in digital …

   SystemVerilog

5. ASIC-ALU-OpenLane ASIC-ALU-OpenLane Public

   ASIC Physical Design using OpenLane – Implementation of a 32-bit ALU at 100 MHz, synthesized, placed, and routed on the SkyWater SKY130 process node using the OpenLane ASIC flow.

   Verilog

6. Custom-RISC-Processor-Logisim Custom-RISC-Processor-Logisim Public

   This repository contains the design files and tools for Ibn-e-Sina, a custom processor architecture designed in Logisim. Alongside the hardware design, it includes a Python-based assembler that con…

   Python